The present invention relates to a signal switching circuit usable in a system including various logical circuits and a signal change-over circuit using such a signal switching circuit or circuits.
FIG. 1 shows a typical signal change-over circuit heretofore employed. In this circuit logical signals S.sub.1, S.sub.2, . . . , S.sub.n output from a plurality of logical circuits 10.sub.1, 10.sub.2, . . . , 10.sub.n are provided via transmission lines 12.sub.1, 12.sub.2, . . . , 12.sub.n to logic gate circuits 20.sub.1, 20.sub.2, . . . , 20.sub.n at one input thereof in a selector circuit 200. The logic gate circuits 20.sub.1 through 20.sub.n are supplied at the other inputs with control signals C.sub.1 through C.sub.n for enabling and disabling them. A desired one of the logic gate circuits 20.sub.1 to 20.sub.n is enabled by one of the control signals C.sub.1 to C.sub.n to select a desired one of the logical signals S.sub.1 to S.sub.n, which is provided to an output terminal 40 via an OR gate 30. Each signal path, which comprises, for example, the logical circuit 10.sub.1, the transmission line 12.sub.1 and the logic gate circuit 20.sub.1, constitutes a signal switching circuit 100.sub.1.
Such a signal change-over circuit is also referred to as a multiplexer and can be used, for example, to output a selected one of clock signals of different frequencies from a plurality of clock signal sources.
The logic gate circuits 20.sub.1 to 20.sub.n which open and close the gate for the logical signals, are not limited specifically to the NAND gates shown in FIG. 1 but may also be various other gate circuits. An ordinary gate circuit is able to control passage of a signal of a frequency between 50 to 70 MHz or so. However, in the case of handling a signal of a frequency higher than 100 MHz, for example, even if the gate circuit is closed, the input signal leaks to the output side of the gate circuit and the leakage level is so high as not to be negligible. That is, in the conventional signal change-over circuit depicted in FIG. 1, for instance, even if the NAND gate circuit 20.sub.1 is held disabled by the control signal C.sub.1, the logical signal S.sub.1 from the transmission line 12.sub.1 leaks to the output side of the NAND gate 20.sub.1 and interferes with other selected logical signals in the OR gate 30.
Further, in the signal change-over circuit shown in FIG. 1 the logical signals S.sub.1 to S.sub.n from the logical circuits 10.sub.1 to 10.sub.n are always present on the transmission lines 12.sub.1 to 12.sub.n regardless of the ON/OFF state of the gate circuits 20.sub.1 to 20.sub.n. This poses another problem as the logical signals S.sub.1 to S.sub.n on the lines 12.sub.1 to 12.sub.n interfere with one another as their frequencies rise.